One of the chief concerns of modern day electronic digital system design is the ability to perform arithmetic functions accurately and quickly. One system for performing the division function is described in U.S. Pat. No. 5,046,038 entitled "METHOD AND APPARATUS FOR PERFORMING DIVISION USING A RECTANGULAR ASPECT RATIO MULTIPLIER" which issued on Sep. 3, 1991 and is assigned to the Assignee of the present invention, the disclosure of which is hereby incorporated by reference into the present application. The advantages attendant with the use of a rectangular aspect ratio multiplier circuit are described in the previously cited patent and in U.S Pat. No. 5,144,579 entitled which issued on Sep. 1, 1992 and is assigned to the assignee of the present application, the disclosure of which is hereby incorporated by reference into the present application.
Using the circuitries and methods described in the previously cited applications, the exact division function can be performed quickly and accurately in a minimal number of clock cycles compared to prior methods. The previously cited exact division methods return both a full precision quotient and a corresponding exact remainder using the rectangular aspect ratio multiplier and an iterative large radix division process. A full precision quotient denotes a partial quotient whose bit length is essentially the same as that of the dividend and divisor, with the possible augmentation by appropriate guard and round bits, and whose value differs from the infinitely precise quotient by less than one unit in the last place. As described in the previously cited applications, each successive large radix quotient digit calculation requires two multiplication steps thus employing two successive passes through the rectangular aspect ratio multiplier. For many applications, including the determination of rounded full precision quotients under a variety of prescribed infinitely precise roundings as specified in the IEEE/ANSI 754 and 854 floating point standards, it is sufficient to provide a sharp division function. The sharp division function returns a full precision quotient and the "sense" of the corresponding exact remainder. The sense of the corresponding exact remainder may be defined as an indicator denoting whether the exact remainder is strictly positive, zero, or strictly negative. For a sharp division function of this type, the clock cycle count for the entire operation can be greatly reduced using the techniques of prescaling of the operands in combination with the concept of a short reciprocal which is described fully in the previously cited U.S. Pat. Nos. 5,046,038 and 5,144,579. Previous teachings on prescaled division have prescribed its use for enhancing methods such as SRT division where two to four bits of the quotient are determined in each clock cycle using shift and add procedures. The prescaling method has also been described with regards to multiple precision arithmetic implemented in software, where a multiplicity of arithmetic operations must be performed in each iteration to effect the extension of the quotient by a unit length typically of the order of the machine word size.
Accordingly, a need has arisen for methods and circuits which are capable of performing large radix prescaled division operations to return the full precision quotient and the sense of the remainder in a minimum amount of clock cycles.